Typ

Artikel in einem Journal

Gebiet

Detektorentwicklung

Autor

Y. Fu, …, C. Brezinaa, K. Desch (für die T. Poikelab, X. Llopartb, M. Campbellb, D. Massimilianob, V. Gromovc, R. Kluitc, M. van Beauzekomc, F. Zapponc and V. Zivkovicc-Kollaboration)

Titel

The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

Datum

2014-01

Reportnummer

2014 JINST 9 C01052

Kurzfassung

Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256 × 256 pixels organized in a square pixel-array with 55 μm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

Journal

doi:10.1088/1748-0221/9/01/C01052